- Lam Research is the Platinum Sponsor of the 27th SEMICON Taiwan Gathering from September 14th to 16th.
- More than 45,000 attendees visited 2,450 booths, showcasing the latest industry trends and technological advancements.
Lam’s experts were invited to SEMICON Taiwan to give keynote speeches at MEMS & Sensor Forum, Smart Manufacturing Forum, IC Forum and Heterogeneous Integration Global Summit. Lam was also invited to speak at the Workforce Development Program – Women in Semiconductor (WiS) Symposium to discuss women’s leadership in STEM.
The following is a recap of key presentations from Lam Research participants at SEMICON Taiwan 2022.
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MEMS and Sensors Forum
In his presentation, “Solving High-Volume Manufacturing Challenges and Technology Changes in MEMS,” David Haynes, Vice President of Strategic Marketing, Customer Support Business Group at Dr. Lam Research, stated that MEMS sensing devices are rapidly evolving into a new frontier of smart sensors.
- MEMS are expected to gain wider application in the automotive, IoT, 5G, smart home and other markets.
- Additionally, MEMS and MEMS fabrication technologies are expected to play a key role in enabling virtual worlds.
Lam Research has developed three strategies to help customers overcome the high-volume manufacturing challenges of MEMS:
- Leveraging Lam’s Leading Technology for MEMS Process Capability
- Addressing high-value challenges for MEMS and sensor customers
- Become a partner for MEMS and sensor development and process optimization
Haynes noted that Lam Research launched Syndion® product family for 300mm wafers and is developing a new generation of DSiE technology specifically for the needs of the MEMS market.
- In addition, Lam is actively investing in the development of new materials, life extension of production tools and scalability of 200-300mm.
The industry is also developing a new generation of piezoelectric MEMS devices to drive a paradigm shift in MEMS devices. Since piezoelectric materials are non-volatile materials used in the etching process, they are more difficult to manufacture.
PhD. Joseph Ervin, Senior Director of Semiconductor Software Products at Lam Research, discusses challenges and solutions in a presentation titled “Using Digital Twins, Predictive Process Models, and Advanced Materials Engineering in Next Node Semiconductor Development” at 3 p.m. and beyond.
By using 193nm immersion lithography (193i) with multiple patterns, chipmakers have been able to produce advanced features down to 7nm, Ervin explained. Using 193i lithography is becoming increasingly problematic at 5nm and beyond due to the large number of patterning and process steps required on smaller feature sizes.
- With the advent of extreme ultraviolet (EUV) lithography, it is now possible to pattern the most difficult features at 3nm and beyond.
- As a result, EUV has become the industry choice for the latest node patterning as it improves dimensional resolution and simplifies patterning and processing.
Unfortunately, transitioning to EUV lithography exposure may not be enough by itself. 193i is a long-lived lithography technology, and lithographic scaling on 193i alone is not enough to scale logic on earlier semiconductor nodes.
- 193i lithography requires different integration techniques, such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP), dicing blocks, material innovations, design technology co-optimization (DTCO), self-aligned patterning, and others. of.
- The patterning specifications for the 3nm process are extremely challenging, and the process is close to physical boundaries. Yield can be affected by unwanted variations and randomly induced defects during EUV processing, resulting in unexpected line edge roughness (LER), line width roughness (LWR), and edge placement error (EPE).
- Compounding these issues, lithography, patterning, and downstream processes must be optimized together to achieve acceptable yield and cost results.
Predictive process models, digital twins, automated variability control, and material optimization techniques can be used to develop next-generation devices using EUV lithography.
- 3nm and below will continue to require material innovation, overall patterning, integration, manufacturing control and DTCO, even with EUV lithography.
- By combining EUV dry resist technology, advanced process models, overall patterning and co-optimized integration, Ervin said EUV lithography should be able to scale to 3nm and beyond.
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PhD. Yang Pan, vice president of Lam Research Advanced Technology Development Company, introduced “Dry Photoresist System for EUV Patterning”, saying that Lam’s dry photoresist deposition and dry development technology is a breakthrough for next-generation logic and DRAM devices Sexual approach is expected to help enable everything from machine learning and artificial intelligence to mobile devices.
- EUV dry resists excel in EUV absorption, fundamental unit size, randomness and pattern collapse.
- EUV dry resist systems achieve superior performance and cost through co-optimization of unit processes.
- “This innovative technology breaks down the trade-off between dose, roughness and defect performance,” Pan said.
To achieve extremely low EUV patterning defects at low doses, Lam Research devised a holistic approach that co-optimizes the complete EUV patterning process through key differentiated steps such as dry photoresist deposition, post-exposure bake (PEB) ), dry development and pattern transfer etching.
- Dry photoresists can provide simple, uniform, and stable metal oxide network compositions after deposition, EUV exposure, and PEB.
- The material contrast of dry photoresists is enhanced by proprietary primer technology and PEB optimization to improve selectivity for dry development and downstream pattern transfer etch.
- Dry development allows Lam to adjust conditions during pattern development to provide optimal dry photoresist integrity and reduce any residue of patterned defect performance.
- Compared to traditional photoresist processes, dry development consumes five to ten times less energy and raw materials, providing key sustainability advantages.
Pan further explained that Lam’s dry EUV patterning system can be extended to use high numerical aperture extreme ultraviolet lithography (NA EUV) technology to define the pitch of posts and holes for future logic and memory technologies.
Integrate Global Summit
In recent years, heterogeneous integration has driven packaging innovations for high-end applications such as application processors () and high performance computing (high performance computing). These applications drive smaller features in the fan-out wafer-level packaging (FO-WLP) and substrate markets. To provide better cost-effectiveness and expand the application range of fan-out technology, fan-out panel-level packaging (FO-PLP) has become another option for chipmakers.
- However, panel-level processes still have many difficulties to overcome.
- John Ostrowski, Managing Director of SABER 3D at Lam Research, addressed these issues in his presentation “Device Challenges for Panel-Level Processing.”
Ostrowski said that due to the immature low-cost fan-out process technology on the panel, the yield rate is low, which limits the market size of FO-PLP. The industry has not yet invested heavily in the research and development of FO-PLP.
- Because the market is small and there is no clear path to increasing production, few companies are willing to invest significant R&D dollars to solve these production problems.
According to Ostrowski, the technical requirements for FO-PLP and substrates are converging, and the volume and growth of the substrate market is significant. The convergence of the two panel markets is expected to create the volume needed to allow more R&D investment into the panel market to help address key issues limiting production.
- Therefore, investment should increase as production increases, and increasing panel production should drive more panel production in a positive feedback loop.
Another problem with panel-level packaging is the lack of standards. Traditionally, many different sized panels have been used in industry. This problem seems to be resolving itself. For substrates, 510mmx515mm and FO-PLP 600mmx600mm panels are becoming the norm.
- In addition to panel size, interface and device standards are also important to allow a common set of devices to be used for both applications.
Ostrovski notess Convergence of substrate and FO-PLP technical requirements will lead to This Adopt more standards. Our work will revolve around developing a common system platform to reduce costs and address challenges including defect control, uniformity control, productivity and cost effectiveness.
Workforce Development Program – Women in Semiconductor (WiS) Symposium
The theme for this year’s Women in Semiconductor (WiS) Symposium is “Unlocking the Potential of Women in Leadership.” Outstanding female executives such as Annie Chou, director of spare parts operations and logistics at Lam Research, were invited to discuss and share their work experience in the semiconductor industry.
- Zhou, who previously worked in Lin’s finance department, stepped out of her comfort zone when joining a job rotation program to support internal and external clients on the front lines.
- She encourages women in the industry to seize the opportunity and create a better career.
Read the interview with Soon Kuek, Head of Operations, Lam Malaysia, and Alyson Crafton, Head of Global Information Systems (GIS) Common Services Organization
As the semiconductor industry continues to develop along “More Moore” to 3nm and beyond, as well as to create “More than Moore” opportunities for heterogeneous integration and special processes, Lam Research showcased its technical prowess at SEMICON Taiwan 2022.
Lam continues to invest in advanced process development, EUV dry photoresist, high volume manufacturing of MEMS and heterogeneous integration in response to industry trends. Lam Research will unswervingly pursue innovation, push the boundaries of technological limitations, and develop solutions that keep semiconductor manufacturing moving forward.
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Frances Huang works in communications and is based in Taiwan
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